1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a driving circuit and method for a liquid crystal display device.
2. Discussion of the Related Art
As information technologies rapidly develop, flat panel display devices develop with such pace. A liquid crystal display (LCD) device, which has been researched and developed in such rapid way, is an example of the flat panel display device.
A typical LCD device includes an upper substrate, a lower substrate, and an interposed liquid crystal therebetween. The upper and lower substrates respectively have electrodes opposing each other. When an electric field is applied between the electrodes of the upper and lower substrates, molecules of the liquid crystal are aligned according to the electric field. By controlling the above-mentioned electric field, the liquid crystal display device provides various transmittances for rays of light such that an image is displayed.
A driving method for driving the LCD device is classified into a passive matrix driving method and an active matrix driving method. The passive matrix driving method uses a voltage difference induced between a data line (a video line) and a gate line (a scanning line). Whereas, the active matrix driving method uses a switching element, usually a transistor. Presently, an active matrix LCD (AM LCD) device adopting the active matrix driving method is most focused on because of its high resolution and superiority in displaying video data.
A typical AM LCD device has a plurality of switching elements and pixel electrodes, which are arranged in the form of a matrix on the lower substrate. Therefore, the lower substrate of the AM LCD device is sometimes referred to as an array substrate. On the upper substrate of the AM LCD device, a common electrode made from a transparent conductive material is usually formed. In case of a color LCD device, a color filter is further formed between the upper substrate and the common electrode. The above-mentioned lower substrate and the upper substrate are attached to each other using a sealant. A liquid crystal is interposed between the upper and lower substrates.
The pixel electrode on the lower substrate and the common electrode on the upper substrate form a liquid crystal capacitor. A data signal and a common signal are respectively applied to the pixel electrode and the common electrode. Then, a voltage difference is induced therebetween such that the liquid crystal capacitor is electrically charged. At this point, electric discharges generally occur at the liquid crystal capacitor until a next data signal is applied. To prevent the above-mentioned discharges such that the voltage difference therebetween maintains its value, a storage capacitor is usually connected with the liquid crystal capacitor. The storage capacitor further serves to stabilize gray level displays and prevent flicker and residual images.
There are two possible configurations for the above-mentioned storage capacitor. A first configuration includes a capacitor electrode on the lower substrate connected to the common electrode on the upper substrate. In the second configuration, a portion of the gate line is used as an electrode of the storage capacitor. Specifically, a portion of an (n−1)th gate line is used as the electrode of the storage capacitor for an nth pixel. The first configuration is referred as a “storage-on-common” structure or an independent storage capacitor type. The second configuration is referred as a “storage-on-gate” structure or a previous gate type.
FIGS. 1 and 2 respectively show the above-mentioned first and second configurations for the storage capacitor. FIG. 1 is a circuit diagram illustrating an equivalent circuit for the independent storage capacitor type, and FIG. 2 is a circuit diagram illustrating an equivalent circuit for the previous gate type.
As shown in FIG. 1 for the independent storage capacitor type, a plurality of gate and data lines 11 and 12 are perpendicularly disposed crossing each other. A TFT 13, a liquid crystal capacitor 14, and a storage capacitor 15 are disposed in a pixel region “P” defined by the crossing gate and data lines 11 and 12. The storage capacitor 15 and liquid crystal capacitor 14 form a parallel circuit therebetween. The independent storage capacitor type has an advantage of a short signal delay.
As shown in FIG. 2 for the previous gate type, a plurality of gate and data lines 21 and 22 are also perpendicularly disposed crossing each other. A TFT 23 is disposed in a pixel region “P” defined by the crossing gate and data lines 21 and 22. The TFT 23 serves as a switching element. A liquid crystal capacitor 24 is further disposed in the pixel region “P” and is electrically connected with the TFT 23, and a storage capacitor 25 is disposed adjacent to the liquid crystal capacitor 24. Here, the storage capacitor 25 is not connected to a gate line Gn that applies signals to the TFT 23 connected with the corresponding liquid crystal capacitor 23. The storage capacitor 25, however, is connected to a previous gate line Gn−1 that precedes the above-mentioned gate line Gn which applies signals to the TFT 23 connected with the corresponding liquid crystal capacitor 23. Thus, the storage capacitor 25 is disposed between the previous gate line Gn−1 and the liquid crystal capacitor 24.
As previously mentioned, the above-described previous gate type uses a portion of the previous gate line as an electrode of the storage capacitor. The previous gate type has advantages of a high aperture ratio and a high production yield.
A typical LCD device adopting the previous gate type, however, needs an additional dummy gate line 26 arranged above a first gate line G1, because there is no previous gate line preceding the first gate line G1. Thus, the dummy gate line 26 is additionally formed above the first gate line G1, and a portion thereof is used as an electrode of the storage capacitor 25 connected with the liquid crystal capacitor 24 in a first pixel region “P1”.
For the typical LCD device adopting the previous gate type, pulse signals are sequentially applied to all the gate lines (reference 21 of FIG. 2), as shown in FIG. 3. Each of the signals has a high period, where the voltage thereof is highest, and a low period. Whenever each of the pulse signals is “high”, a corresponding TFT 23 is “on”. Whenever each of the pulse signals is “low”, a corresponding TFT 23 is “off”. Preferably, a positive voltage signal is applied for the high period, and a negative voltage signal is applied for the low period. Hereinafter, the pulse signal applied to the gate line 21 is referred to as a gate signal. Each of the above-mentioned gate signals preferably includes just one pulse during one frame. The pulse of each gate signal preferably has a different timing from those of the others, and the period of the pulse is the same as a horizontal line period “1H”.
As previously mentioned, the dummy gate line 26 is additionally formed above the first gate line “G1”. When a first gate signal is applied to the first gate line G1, the TFT “23” is “on” such that a data signal is applied to a pixel electrode (not shown) via the data line 22. To charge the storage capacitor 25 connected to the dummy gate line 26, a dummy signal is further applied to the dummy gate line 26. At this point, the gate signal applied to the gate line 21 includes a high period and a low period, and the low period is much longer than the high period. Therefore, the dummy signal applied to the dummy gate line 26 conventionally has a negative voltage corresponding to the low period of the gate signal without regard to the high period thereof.
Moreover, the dummy gate signal is conventionally different from the gate signal in that the gate signal has a pulse of a high period, for example, but the dummy gate signal only has a low period. Because of the above-mentioned difference, the storage capacitor 25 connected to the dummy gate line 26 has a different charging characteristic from the others. Thus, liquid crystal molecules disposed over the first gate line “G1” have a different aligning characteristic from those of the other molecules disposed over the other gate lines. This difference in the first gate line causes a non-uniform brightness at the first line of the display.